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Come, join us for a FREE Hands-on Workshop on VLSI Design using Verilog HDL on Sun, 2nd June.
Venue: Maven Silicon Campus, Bannerghatta Road
Time: 9 AM to 1 PM
How this workshop can help you?
This workshop will help you to understand the concepts of RTL design using Verilog HDL and also empower you with hands-on experience.
Highlights of the Workshop :
Seats are limited. Hurry...
Overview of VLSI Design | RTL Design using Verilog HDL | Verilog Labs | Quiz | Participation Certificate & more...
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